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Thermal Management Key to Next-Generation Chip Breakthroughs
Semiconductor devices are going vertical. 3D chip stacking has already shown up in memory devices and smartphone cameras. Processors for artificial intelligence (AI) apply 2.5D technologies. Thermal challenges are the main bottleneck to wider commercialisation of true 3D integrated circuits (3D-ICs).
Moore’s Law was that the number of transistors on a microchip would double every two years. The prediction by Intel’s co-founder held for many decades, but staying on the same exponential growth path required a paradigm shift in semiconductor design. Semiconductor devices had to go vertical. Multiple chips are now stacked on top of each other into one single package with shorter interconnects on a smaller footprint. 3D stacking has been gaining traction in applications that require extreme performance, power efficiency and miniaturisation.
Leading chip manufacturers including Intel, AMD, Samsung and Nvidia have introduced products that use 3D integrated circuits (3D-IC) technology. Intel has integrated their die-to-die packaging technology Foveros into some of their latest processors. Samsung invests in 3D packaging technologies like X-Cube for high-density interconnects. Major foundries like TSMC (Taiwan Semiconductor Manufacturing Company) and GlobalFoundries are investing in 3D-IC capabilities. TSMC has advanced packaging technologies like Chip-on-Wafer-on-Substrate (CoWoS) and 3D Fabric.
3D stacking has been emerging in different categories of applications. Stacked memory or High Bandwidth Memory (HBM) is already widely used in applications like 3D NAND flash drives. AMD uses HBM on top of GPUs and CPUs. Micron and Samsung are other key players in 3D NAND and other forms of memory stacking technology. Another mature 3D-IC product category is CMOS imagers stacked on top of processors in smartphones.
One of the most active areas of research and development in 3D integration is artificial intelligence (AI) computational units. These require a close connection between the memory and the logic components. Nvidia, the leader in graphics processing units (GPUs) and AI technology, uses 3D-IC technology with HBM on GPUs, advanced interconnect technologies NVLink and NVSwitch and AI accelerators with heterogeneous integration of different types of chips in a single package, involving both 3D stacking and advanced 2.5D techniques.
2.5D is an intermediate step towards 3D-IC where the logic and memory sit next to each other on a silicon interposer, a piece of material with circuitry that interconnects different types of chips. Stacking memory is relatively simple, because all the chips can have the same size and power. Stacking memory on logic is more challenging, because the chiplets have different sizes and power coefficients. The 2.5D configuration is used mainly for thermal reasons – Nvidia also invests heavily in cooling solutions and advanced thermal interface materials (TIMs) to get to true 3D-ICs.
The thermal problem of 3D-ICs is the increased power density in the stacked package and the difficulty of dissipating heat from between the layers through limited pathways. Variations in temperatures across different layers or regions of the 3D stack can create thermal gradients that can cause mechanical stresses due to differences in thermal expansion, potentially breaking interconnects.
In Europe the Belgium-based research institution Imec (Interuniversity Microelectronics Centre) plays a central role in working on these problems, along with CEA-Leti in France and Fraunhofer in Germany. Imec has a large research program on 3D chip stacking, looking at all aspects of advanced packaging and 3D integration, including design enablement, material compatibility, processing, mechanical and thermal. Imec collaborates with all the major semiconductor companies, from foundries and chip companies to materials and tool suppliers.
Microfluidic cooling could be part of the solution to the thermal challenges in 3D-ICs. Coolant would remove heat via microchannels within the chiplet and out with Through-Silicon Vias (TSVs) in the layers. Advancements in thermal interface materials (TIMs) will also play a role in solving the thermal problems. Dynamically adjusting power based on workload, or Dynamic Voltage and Frequency Scaling (DVFS), could mitigate heat generation. Before thermal solutions can be designed and validated in experiments, sophisticated modelling and simulation tools are required to understand what actually happens within the chip stack.
JOIN US AT THERMAL MANAGEMENT EXPO EUROPE, STUTTGART, GERMANY, 3-5 DECEMBER
Herman Oprins, R&D Team Leader Thermal Modeling at Imec; Cor Rops, Senior Scientist Thermal and Fluidic Engineering at TNO and Jason Hoffman-Bice, Co-founder and CEO at Fourier LLC, will discuss the thermal challenges in 3D stacking in a webinar on July 18, 2024. The topic will also be covered on a panel at the next Thermal Management Expo conference, 3-5 December in Stuttgart.